A new extrinsic dc model for high speed lattice matched InAlAs/InGaAs/InP HEMT with a predicted 135 GHz cut-off frequencyJOGI, Jyotika; GUPTA, Mridula; GUPTA, R. S et al.Microelectronics journal. 2001, Vol 32, Num 12, pp 925-930, issn 0959-8324Article

Impact of Temperature and Indium Composition in the Channel on the Microwave Performance of Single-Gate and Double-Gate InAlAs/InGaAs HEMT : NanoCon 2012BHATTACHARYA, Monika; JOGI, Jyotika; GUPTA, R. S et al.IEEE transactions on nanotechnology. 2013, Vol 12, Num 6, pp 965-970, issn 1536-125X, 6 p.Article

Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysisGAUTAM, Rajni; SAXENA, Manoj; GUPTA, R. S et al.Microelectronics and reliability. 2012, Vol 52, Num 6, pp 989-994, issn 0026-2714, 6 p.Article

Analytical non-linear charge control model for InAlAs/InGaAs/InAlAs double heterostructure high electron mobility transistor (DH-HEMT)GUPTA, Ritesh; SANDEEP KUMAR AGGARWAL; GUPTA, Mridula et al.Solid-state electronics. 2005, Vol 49, Num 2, pp 167-174, issn 0038-1101, 8 p.Article

Channel thermal noise of SOI MOSFET in high-frequency regionKAPOOR, Nirupama; HALDAR, Subhasis; GUPTA, Mridula et al.Semiconductor science and technology. 2005, Vol 20, Num 2, pp 216-220, issn 0268-1242, 5 p.Article

Two-dimensional analytical modeling and simulation of retrograde doped HMG mosfetGUPTA, R. S; GOEL, Kirti; GUPTA, Mridula et al.IEEE Lester Eastman conference on high performance devices. 2004, pp 52-59, isbn 981-256-196-X, 1Vol, 8 p.Conference Paper

Temperature dependent subthreshold model of long channel GAA MOSFET including localized charges to study variations in its temperature sensitivityGAUTAM, Rajni; SAXENA, Manoj; GUPTA, R. S et al.Microelectronics and reliability. 2014, Vol 54, Num 1, pp 37-43, issn 0026-2714, 7 p.Article

Numerical Model of Gate-All-Around MOSFET With Vacuum Gate Dielectric for Biomolecule DetectionGAUTAM, Rajni; SAXENA, Manoj; GUPTA, R. S et al.IEEE electron device letters. 2012, Vol 33, Num 12, pp 1756-1758, issn 0741-3106, 3 p.Article

Simulation study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for high temperature applicationsKUMARI, Vandana; SAXENA, Manoj; GUPTA, R. S et al.Microelectronics and reliability. 2012, Vol 52, Num 8, pp 1610-1612, issn 0026-2714, 3 p.Conference Paper

An analytical charge-based drain current model for nano-scale In_0.52Al_0.48As-In_0.53Ga_0.47 as a separated double-gate HEMTRATHI, Servin; JOGI, Jyotika; GUPTA, Mridula et al.Semiconductor science and technology. 2010, Vol 25, Num 11, issn 0268-1242, 115003.1-115003.9Article

An analytical model for discretized doped InAlAs/InGaAs heterojunction HEMT for higher cut-off frequency and reliabilityGUPTA, Ritesh; AGGARWAL, Sandeep K; GUPTA, Mridula et al.Microelectronics journal. 2006, Vol 37, Num 9, pp 919-929, issn 0959-8324, 11 p.Article

Numerical modelling and simulation of non-uniformly doped channel 6H-silicon carbide MOSFETKAUSHIK, Navneet; HALDAR, Subhasis; GUPTA, Mridula et al.Semiconductor science and technology. 2004, Vol 19, Num 3, pp 373-379, issn 0268-1242, 7 p.Article

Numerical analysis of localised charges impact on static and dynamic performance of nanoscale cylindrical surrounding gate MOSFET based CMOS inverterGAUTAM, Rajni; SAXENA, Manoj; GUPTA, R. S et al.Microelectronics and reliability. 2013, Vol 53, Num 2, pp 236-244, issn 0026-2714, 9 p.Article

Comparative Study of Silicon-on-Nothing and III―V-on-Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications : NanoCon 2012KUMARI, Vandana; SAXENA, Manoj; GUPTA, R. S et al.IEEE transactions on nanotechnology. 2013, Vol 12, Num 6, pp 978-984, issn 1536-125X, 7 p.Article

Immunity against temperature variability and bias point invariability in double gate tunnel field effect transistorNARANG, Rakhi; SAXENA, Manoj; GUPTA, R. S et al.Microelectronics and reliability. 2012, Vol 52, Num 8, pp 1617-1620, issn 0026-2714, 4 p.Conference Paper

Scattering parameter based modeling and simulation of symmetric tied-gate InAlAs/InGaAs DG-HEMT for millimeter-wave applicationsBHATTACHARYA, Monika; JOGI, Jyotika; GUPTA, R. S et al.Solid-state electronics. 2011, Vol 63, Num 1, pp 149-153, issn 0038-1101, 5 p.Article

Unified model for physics-based modelling of a new device architecture : triple material gate oxide stack epitaxial channel profile (TRIMGAS Epi) MOSFETGOEL, Kirti; SAXENA, Manoj; GUPTA, Mridula et al.Semiconductor science and technology. 2007, Vol 22, Num 4, pp 435-446, issn 0268-1242, 12 p.Article

Gate-All-Around Nanowire MOSFET With Catalytic Metal Gate For Gas Sensing Applications : NanoCon 2012GAUTAM, Rajni; SAXENA, Manoj; GUPTA, R. S et al.IEEE transactions on nanotechnology. 2013, Vol 12, Num 6, pp 939-944, issn 1536-125X, 6 p.Article

Dielectric Modulated Tunnel Field-Effect Transistor: A Biomolecule SensorNARANG, Rakhi; SAXENA, Manoj; GUPTA, R. S et al.IEEE electron device letters. 2012, Vol 33, Num 2, pp 266-268, issn 0741-3106, 3 p.Article

Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment AnalysisRUPENDRA KUMAR SHARMA; GUPTA, Ritesh; GUPTA, Mridula et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 6, pp 1284-1291, issn 0018-9383, 8 p.Article

Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance-Part I: Impact of Gate Metal Workfunction EngineeringKASTURI, Poonam; SAXENA, Manoj; GUPTA, Mridula et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 1, pp 372-381, issn 0018-9383, 10 p.Article

Graded channel architecture : the solution for misaligned DG FD SOI n-MOSFETsRUPENDRA KUMAR SHARMA; GUPTA, Ritesh; GUPTA, Mridula et al.Semiconductor science and technology. 2008, Vol 23, Num 7, issn 0268-1242, 075041.1-075041.14Article

Multi-material gate poly-crystalline thin film transistors : Modeling and simulation for an improved gate transport efficiencySEHGAL, Amit; MANGLA, Tina; GUPTA, Mridula et al.Thin solid films. 2008, Vol 516, Num 8, pp 2162-2170, issn 0040-6090, 9 p.Article

Two-dimensional analytical threshold voltage model for DMG Epi-MOSFETGOEL, Kirti; SAXENA, Manoj; GUPTA, Mridula et al.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 1, pp 23-29, issn 0018-9383, 7 p.Article

Gate All Around MOSFET With Vacuum Gate Dielectric for Improved Hot Carrier Reliability and RF PerformanceGAUTAM, Rajni; SAXENA, Manoj; RADHEY SHYAM GUPTA et al.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 6, pp 1820-1827, issn 0018-9383, 8 p.Article